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you can code the X1 to the metal just like you can code PS4 to the metal. X1's problems are its design, not the OS. if she thinks of Win 8 as a heavy layer then she might as well call the 3GB reserve FreeBSD OS on PS4. in the end, both are reserving about the same GBs of RAM. so i don't get the problem.
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Title says tiling and detiling.
Whether it is GPU based of CPU based is irrelevant to this topic or rumor that PS4 couldnt do it. Rumor was ludicrous anyways given how the AMD GPU PS4 was based off of had some dedicated hardware for tiling on GPU. Sony decides to go with CPU route since they thought it was more efficient on CPU with another dedicated hardware on it.
03-06-2014 #54PSN: Metfanant
Tiled resources - The management of what textures or assets actually need to be loaded up as they are on screen
Tiled rendering - Way of breaking up the frame into tiles and only having to render parts that have changed.
Very basic way of putting it but they are different things.
There are so many different things developers can tile.
Apparently Cort is talking about texture swizzling. (yes, I follow him too.)
Perhaps something like this.
jlippone likes this post
so what i'm getting is, they don't need to tile on the PS4 but if they want super textures/resources...then they can. whereas that other console needs it in order to reach its potential. am i close enough?
Only reason to tile something is because you want something to be tiled for a some reason.
Usually the reason for a tiling/swizzling is for cache efficiency.
This has nothing to do on different consoles, it's same on all systems which have some form of caches. (All CPUs in last ~30 years.)
Simply put, how you store and read your data is important.
My guess would be post processing of some sort, but could just as easily be in regards to any sort of form of trying to read in the texture into the CPU for some reason or another. Textures can store more than just actual "images". You can pack anything into in realistically, it's just a form of data container, with each address being normally 32 bits.
But either way, as I said in my opening remark of all of this its all about cache hit timings.
Getting you data aligned so that it all fits in a cache read line make HUGE improvements to CPU timings.
I don think people fully understand how import L1 and L2 cache is in the context of performance of these CPU's.
really guys, way to make this thread nerdy and lame lol.
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