Article on Cell Architecture

[Schmeh]

http://www.blachford.info/computer/Cells/Cell0.html

I was wondering if anyone else has read this article on the Cell's architecture. I have been trying to follow the news on the Cell since it was first rumored and so far I think this explains it better than anything else out there. It cleared up some misconceptions that I had.

I am not sure how accurate the specs are, but if they are then the Playstion 3 should be able to out perform the X-Box 2 by a wide margin.

[gaming ultima]

yep ive read it as well
though from what i can remember he thought that the local memory for each APU runs at 4.6GHz (the APU's native clockspeed) when infact they run at 4.8GHz, though he might of said 4.8GHz, i cant remember
anyway...
xenon fanboys thought it was 'fake' lol, how can someone saying their opinion based on specified resources be 'fake'? lol

[PeanutButterMunky]

Yes, it's very interesting. However, despite the simplified explanations, I'll be waiting for Sony Representatives to explain the information better.

[SessDMC]

Me too, but an excellent find there, this it exciteing stuff...

[gaming ultima]

we dont have long to wait till the ISSCC which is in earlyish feb where STI are going to be going into details about it

[don_milz]

Recent info has been given about cell:
4.6 GHz
1.3v
85 Celcius operation with heat sink
6.4 Gigabit / second off-chip communication

On top of that my prediction at what Cell would be like is as follows.

This is a 9 core processor, one of these cores is something similar to a PowerPC G5 and acts as a controller. The remaining 8 cores are called APUs and these are very high performance vector processors. Each APU contains it's own block of high speed RAM and is capable of 32 GigaFlops (32bit). The APUs are independent processors and can act alone or can be set up to process a stream of data with different APUs working on different stages. This ability to act as a "stream processor" gives access to the full processing power of a Cell which is more than 10 times higher than even the fastest desktop processors.

Since each APU will do 32Gflops, and there are 8 of them

8*32=256 Gflops from one cell chip.

But then there is the possibilty of PS3 having mutiple cells, 4 of them could do 1 teraflop (1000 Gflops).

In addition to the raw processing power the Cell includes a high performance multi-channel memory subsystem and a number of high speed interconnects for connecting to other Cells or I/O devices.

Above i said 85 degrees, but that is purely from what i have read in the presentation about cell...but considering that with no fan (only heat sink) it was running at 85, i would expect it to run more coolly then the presentation said.

Plus factor in that PS3 is due out in about 18 months...which gives time for better heat solutions.

Another factor is that Sony recently Licenced LongRun 2 from Transmeta.

LongRun has always been a key feature of Transmeta's chip designs, minimising energy consumption and heat dissipation.

....

How Sony will use the technology remains to be seen, but it's certainly tempting to speculate that it plans to use the system to keep 'Cell' running coolly.

http://www.theregister.co.uk/2005/01...sony_longrun2/

So given the time frame, this new longrun 2, and the use of a fan, cell should be running cooler than than your average ice cube

[PeanutButterMunky]

4.6 GHz
1.3v
85 Celcius operation with heat sink
6.4 Gigabit / second off-chip communication

That's not a prediction. That's official information given from Sony.

[don_milz]

4.6 GHz
1.3v
85 Celcius operation with heat sink
6.4 Gigabit / second off-chip communication

That's not a prediction. That's official information given from Sony.

Fair enough...thats not a prediction...but you wouldn't expect me to say something different than what has already been said by sony.

Since that info is already given, it only makes sense to use it.

I have editted my earlier post so not to take credit for claiming it was a prediction when it wasn't.

[SessDMC]

The register to me is an un-trusted source, but it dose make sence (weirly enough) and is Sony going with Vector unit technology again?

[Final_fantasy]

if the article is saying what i think it says, they could put a port in the ps3 for people to add a cell chip or two to make the system better all by themselves. i would like to see that at least

[The_One]

Here's an counter article to what Blachford said:
http://arstechnica.com/news.ars/post/20050124-4551.html

And... Blachford's rebuttal:
http://www.blachford.info/computer/Cells/Rebuttal.html

They're both interesting read. Have fun .

[Shred0r]

some more info on Cell:

"Crowd Simulation on PS3":
http://www.ps3-live.com/divers/crowd-simulation.pdf

"High Performance Physics Solver Design for Next Generation Consoles":
http://www.ps3-live.com/divers/physics.pdf

Make comments if you have found something interesting about the Cell/PS3...

Wasnt quite sure were to put this post...if this topic is not that suitable for this Cell info, whatever...have to check the pdf files for myself yet....

[udontneed2know]

That technica article is probably the worst thing I've ever seen. For a tech website to choke under the pressure of having to talk technically about a new processor it is a rather funny thing to watch.

Half of what technica talks about has FAR more to do about assumptions and lack of information then the Blachford article. Other times, like calling the SPE's SRAM as " scratchpad cache " is blatantly plain stupid and wrong. Its like they don't even know the differences between local storage and cache. Its funny though and its why alot of people just ignore technica these days.

[JordanL]

That technica article is probably the worst thing I've ever seen. For a tech website to choke under the pressure of having to talk technically about a new processor it is a rather funny thing to watch.

Half of what technica talks about has FAR more to do about assumptions and lack of information then the Blachford article. Other times, like calling the SPE's SRAM as " scratchpad cache " is blatantly plain stupid and wrong. Its like they don't even know the differences between local storage and cache. Its funny though and its why alot of people just ignore technica these days.

Yeah, I came to the conclusion about a year ago that arstechnica was a group of glorified geeks that really didn't know much more than the average geek about what they talked about.

[udontneed2know]

Just to show you why technica is pathetic.

hford also declares that the longstanding problems inherent in code parallelism and multithreaded programming are now solved, because the Cell will just miraculously do all this stuff for you via fancy compiler and process scheduling tricks. Unfortunately, parallelization is a fundamental application design problem that's rooted in the inherently serial nature of many of the kinds of tasks that we ask computers to perform. There are good parallelizing compilers out there, but they can only extract parallelism that's already latent in the input code and in the algorithm that the code implements; they can't magically parallelize an inherently serial sequence of steps

Blachford stated that parallelism is solved via Cell considering that Cell has 8 SPE's which through their inherent design are capable of breaking down tasks together, which provides a much more stables parallel programming method then todays tries which consists of trying to parallel program on single cores not built for the task in the first place ( supercomputers have been doing parallel processing for ages due to multiple cores ). Yet Technica tries to derationalize this theory with this god awful mess of yapping in the above quote. Notice they don't talk about Cell, they just talk about todays processors and the problems with parallel programming.

These are just three of the many basic flaws in this article. Furthermore, the article is chock full of wild-eyed and completely unsubstantiated claims about exactly how much butt, precisely measured in kilograms and centimeters squared, that the Cell will kick, and how hard, measured in decibels, that the Cell will rock. I'm as excited about the Cell as the next geek, but there's no need to go way over the top like this about hardware that won't even seen the light of day for a year. And it's especially ill-advised to compare it to existing hardware and declare that we have a hands-down winner.

One hand, im excited about Cell ( this is a year old article BTW, before all the information was out which confirmed Blachfords analysis ), but on the other hand I'll just crap all over someone elses accurate analysis with my own spewing of rabid idiocy. Yeah, that makes sense doesn't it?

It has been speculated that the vector units are the same as the AltiVec units found in the PowerPC G4 and G5 processors. I consider this highly unlikely as there are several differences. Firstly the number of registers is 128 instead of AltiVec's 32, secondly the APUs use a local memory whereas AltiVec does not, thirdly Altivec is an add-on to the existing PowerPC instruction set and operates as part of a PowerPC processor, the APUs are completely independent processors.

The author appears to be confusing an instruction set with an implementation. The 128-register detail is a problem, because, as the author correctly points out, conventional Altivec has only 32 vector registers. So obviously it's a given that Cell won't be using straight-up Altivec. But it's entirely possible that it'll use some kind of 128-register derivative of the Altivec instruction set. The fact that the individual processing units have a local cache has little to do with whether or not the PUs themselves implement some hypothetical Altivec derivative. Finally, the statement, "Altivec is an add-on to the existing PowerPC instruction set," is correct, but the rest of that sentence--"and operates as part of a PowerPC processor"--doesn't make a whole lot of sense to me in this context. Altivec is an ISA extension that is implemented in different ways on different PowerPC processors. The Cell processor's PUs could very well implement a hypothetical 128-register Altivec2 ISA extension, or they could implement some other SIMD ISA extension. The fact that SIMD code, written to whatever ISA, is farmed out to individual PUs has nothing to do with it. (If what I just said confuses you, you might check out this article.)

This part is hilarious. Blachford was stating reasons why the SPU's most likely won't use Altivec, but then this technica geek comes in with a rebuttal pretty much saying the exact same thing. That the SPU's won't be using Altivec. Anyone else see the problem here? lmao.

[Trinity]

DUDE this is like the oldest thread ever. Gaming Ultima and The One were around so thats how old this is.

[AlexPallas]

i like how they said obscene capabilities

[Terarrim]

Been posted quite a few times however the article is very good and he wrote it before much of the testing and benchmarks come out. And he was proven right in his assertions.

[ps3 Wanna be]

This seems ironic considering what Justin has posted lol.

For the next two weeks at least, I'm back to good ol' dialup as I move back to my permanent home. This means I may be slower getting your articles up.

I am praying this doesn't run into TGS.

I won't be able to FTP anything large. This includes large image sets (e.g. for previews), or videos.

Hopefully Rebon will be able to get to some articles as well.

[Rebon]

Hopefully Rebon will be able to get to some articles as well.

I will do my best, although I feel a bit stuck - as I havent been following every new article, and so I can't tell if it has always been posted before.