PS3 "Cell" Unveiled Today

[McLaren]

Read This

Source: Spong.com

As the countdown to today’s Cell presentation, held at the International Solid-State Circuits Conference in San Francisco ticks by, more speculation is emerging as to what may be announced.

Following on from various memo leaks and even what purports to be a presentation slide, comes some in-depth analysis from Tom Halfhill of the Microprocessor Report. Speaking to News.com, Halfhill aims to throw some light on the mysterious Sony, IBM and Toshiba co-developed processor.

For reference, the slide claims a 4.6 GHz clock speed shifting 6.4 GB per second off-chip communication with a CPU temp of 85 degrees C.

The cell has, built in to its design, the idea of distributed processing. A large task can be split across multiple cores on multiple chips on multiple devices across a network. All without the programmer having to worry about it at all. Your TV or stereo could help the PS3 to render a scene if they were based on cell and networked together, an incredible feat if delivered effectively. The cell processor is capable of running different tasks on each of its cores (called software cells) instead of just breaking up the same task across the cores. "The software cells are designed to be kind of self-contained--they can kind of roam around," Halfhill said.

"The Cell architecture is designed to make grid computing almost universal," Halfhill continued. "It makes distributed processing part of the design. If you have several of these machines on a network, the work can be spread across a network."

The cell also has memory protection built in to the chip. A process can only access the memory it is allocated by the system. Normally this is done by the OS, and hence can be got around by naughty code. On cell that's not possible, since the memory divisions are managed by the hardware.

"A lot of [piracy] techniques rely on one application being able to access the same memory region as another application," Halfhill said. "With Cell, you can't do that because memory regions are locked down by the application. What they're doing to fence off this memory requires a lot of memory access," he said. "It looks to me like a pretty cumbersome system. There's got to be some performance hit, and they're going to have to optimize the final design to get around that."

Check back here tomorrow for a full outline of exactly what is announced by Sony, IBM and Toshiba.

Another Source: http://gaming.engadget.com/entry/1234000763030645/

[SessDMC]

FROM BBC.CO.UK

Sony, IBM and Toshiba, who have been working on the Cell processor for three years, will unveil the chip at a technology conference.

The chip is reported to be up to 10 times faster than current processors.

It is being designed for use in graphics workstations, the new PlayStation console, and has been described as a supercomputer on a chip.

Sony has said the Cell processor could be used to bridge the gap between movies and video games.

Special effects and graphics designed for films could be ported for use directly in a video game, Sony told an audience at the E3 exhibition in Los Angeles last year.

'Ideal technology'

Cell could also be marketed as an ideal technology for televisions and supercomputers, and everything in between, said Kevin Krewell, the editor in chief of Microprocessor Report.

The chip will be made of several different processing cores that work on tasks together.

The PlayStation 3 is expected in 2006 but developers are expecting to get prototypes early next year to tune games that will appear on it at launch.

Details of the chip will be released at the International Solid State Circuits Conference in San Francisco.

Some details have already emerged, however.

When put inside powerful computer servers, the Cell consortium expects it to be capable of handling 16 trillion floating point operations, or calculations, every second, if multiple Cell chips were used together.

Detailed graphics

The chip has also been refined to be able to handle the detailed graphics common in games and the data demands of films and broadband media.

IBM said it would start producing the chip in early 2005 at manufacturing plants in the US. The first machines off the line using the Cell processor will be computer workstations and servers.

A working version of the PS3 is due to be shown off in May 2005 but a full launch of the next generation console is not expected to start until 2006.

"In the future, all forms of digital content will be converged and fused onto the broadband network," said Ken Kutaragi, chief operating officer of Sony, said last year.

"Current PC architecture is nearing its limits," he added.

As said, check back tommrow anything on cell should be posted here... keeps the info in one place.

[DezNutz]

Source:ZDNet

PS3 Cell chip aiming high
4 February 2005 15:27 by Dela

The Cell processor that will power Sony's upcoming Playstation 3 is set to be unveiled at the International Solid-State Circuits Conference in San Francisco on Monday, but Tom Halfhill of the Microprocessor Report has an idea of what to expect. He has studied patents and documents relating to Cell and sees a number of chip breakthroughs that dramatically boost computing power in everything from game consoles to mobile phones. Current multicore chips typically chop a single computing task into parts, which are distributed among processing units. Cell's processing units called software cells can handle completely separate jobs.

"The software cells are designed to be kind of self-contained, they can kind of roam around," Halfhill said. Cells are also capable of roaming over a network, allowing the processor to perform a type of distributed or grid computing. So technically a PS3 could borrow processing power from another PS3 console on a network. "The Cell architecture is designed to make grid computing almost universal," Halfhill said. "It makes distributed processing part of the design. If you have several of these machines on a network, the work can be spread across a network."

Cell also has some security features that will help to prevent unauthorised copying and distribution of copyrighted content. For example, it locks down memory regions so only authorised applications can access protected content. However, Halfhill expresses some concern over this security mechanism, hoping that it won’t drastically undercut chip performance. "What they're doing to fence off this memory requires a lot of memory access," he said. "It looks to me like a pretty cumbersome system. There's got to be some performance hit, and they're going to have to optimize the final design to get around that."

Do you think this could mean you could share proccessing on PS3 online?

[n65007]

Sony PS3 Supercomputer Debut Affiliates

By Cornelius Wilson on 02/07/05

The cell "supercomputer" chip that powers the new PlayStation 3 games console is set to be unveiled today in San Francisco.

Sony, IBM and Toshiba have spent some $400 million developing the next generation cell chip for the past three years.

It is thought the super chip will be able to process a whopping 256 billion operations a second making the new chip around ten times faster than current processors.

The Times explains how it works: Whereas most existing microchips contain several cores that all work on the same task, the new chip is divided into entirely separate "cells" that can work independently on different tasks. What this means in practice is that computers linked together in a network can borrow unused processing power from each other, making the most efficient use of their computing capabilities. For example, if two PlayStation 3 consoles were connected via the internet, one could use part of the other's Cell chip to complete processor-intensive tasks such as downloading video content.

[SessDMC]

This means that when the BD-rom is inserted into your 'ps3' it load up the tasks that the 'cell' has to do, like handel this to one APU and handel the other to another APU, quite smart if you ask me and for downloading movies the unused processing power is like 2+2=4 if you think about it, you add both raw processing powers from each PS3 and then voila you have extreame performance, this is what sonys is wanting, i can remember reading back a few weeks about sony wanting to have the largest gameing network, or something or other on them lines to do with the ps3. but lets wait for tommrow... i think we got all the info we can get today (otherwise we would be like a broken record player) but its going to be mad tommrow!

[DezNutz]

Source : http://www.extremetech.com/article2/...1761407,00.asp

"We are confident that Cell will provide major momentum for the progress of digital convergence, as a core device sustaining a whole spectrum of advanced information-rich broadband applications, from consumer electronics, home entertainment through various industrial systems," said Masashi Muromachi, corporate vice president of Toshiba Corporation and president and chief executive of Toshiba's Semiconductor Company, in a statement.

In the lab, the trio of companies said they'd pushed the Cell over 4-GHz, although each individual OEM will decide how best to implement the chip. The prototype Cell chip is 221 sq. mm, integrates 234 million transistors, and is fabricated with 90 nanometer SOI technology at IBM's fabrication plant in East Fishkill, N.Y. Sony will begin fabricating the chip at its Nagasaki facility later this year.


The Cell processor uses two technologies from Rambus: a chip-to-chip interconnect, FlexIO, formerly known as "Redwood"; and an eXtended Data RAM (XDR) interface. Sony indicated in January 2003 that it would use the FlexIO and XDR technology in future game consoles in conjunction with the Cell microprocessor.

The FlexIO technology will be used to connect the various chips on a Cell-based motherboard, according to Rich Warmke, marketing director of the memory interface division at Rambus. A multicore Cell processor, by contrast, will use its own internal bus to connect multiple cores. However, 90 percent of the Cell's external pins are connected to either the FlexIO or XDR interfaces, evidence that the Cell's design emphasizes moving application and or 3D scene data around within main memory, Warmke said.

In total, the two interfaces combined can offer up to 100 Gbytes per second of total bandwidth, an order of magnitude above some other devices, Warmke said. For example, Nvidia's fastest GeForce 6800 Ultra graphics chip allocates 35.2 Gbytes/sec through its dedicated memory interface, which uses a specialized version of standard double-data-rate (DDR) memory called GDDR-3.

"It's more bandwidth than I've ever heard of," Warmke said.

The FlexIO interface runs at 6.4-GHz, while the XDR interface runs at half of that speed, or 3.2-GHz. Warmke declined to offer specifics on the bandwidth mismatch. "We worked with Sony to understand their needs," he said. "With that application, that ratio of bandwidth was appropriate. Other applications may require more memory bandwidth and less chip-to-chip bandwidth."

Finally, the Cell chip was also designed to be an "OS-agnostic processor," capable of running real-time operating systems, "guest" applications, and Linux. The flexibility will allow the Cell to be designed into a variety of products, the companies said.

[SessDMC]

Apart from that we might not be a broken record yet lol, looks like there will be more emphesis on linux this time maybe? could happen. and there are some number there that are incredibly exiteing! (i know what they mean) this will be a real step from the PS brand in graphical power bandwidth.

[evanft]

http://www.gamespot.com/news/2005/02...s_6118072.html

Engineers from Sony, IBM and Toshiba unveil the Cell processor which will be the heart of the next-generation console.

The chip that will run the next version of the PlayStation video game machine will have nine processor cores and run faster than 4GHz, the chip's designers revealed Monday.

Engineers from Sony, IBM and Toshiba revealed those and other specifications for the Cell processor during a press conference at the International Solid State Circuits Conference, where technical papers on the Cell design will be presented this week.

The three companies have been working on the Cell for several years, promising to deliver a high-performance chip optimized for multimedia applications. Test production of Cell chips is set to begin later this year, and the processors will appear later in workstation PCs optimized for animation and other graphics chores. The chip will also power the next version of Sony's PlayStation game console, which is widely expected to be released late this year or early next year.

While analysts and researchers have already puzzled out most of the basic aspects of the Cell design, Monday's announcements included some of the first specifics.

The Cell will have a 64-bit Power processor and eight "synergistic processing units" capable of handling separate computing tasks, said Jim Kahle, an IBM fellow. The multicore design will give software developers tremendous flexibility, Kahle said, allowing them to run multiple operating systems on the same chip and experiment with variations on grid computing.

"It's designed from the beginning to work in a world where all the computers are tied together," he said.

Future versions of Cell chips could have more or fewer processing units depending on what device and software designers require, Kahle said. "There are a number of different ways to implement parallelism on the chip," he said.

How those processing units are used is up to software developers, including the game makers who will soon start wrestling with the PlayStation 3. Kahle said IBM and its Cell partners will provide game developers and other code writers with open-source tools and guidelines for working with Cell, but game developers will have final say on how they chop up computing tasks among the processing units.

"It's really...up to the game developer," he said. "You can program it in many different ways."

Other Cell numbers include the following:

• The first version of the chip will run at speeds faster than 4GHz. Engineers were vague on how much faster, but reports from design partners say 4.6GHz is likely. By comparison, the fastest current Pentium PC processor tops out at 3.8GHz.

• Cell can process 256 billion calculations per second (256 gigaflops), falling a wee bit short of marketing hyperbole calling it a "supercomputer on a chip." The slowest machine on the current list of the Top 500 supercomputers can do 851 gigaflops.

• The chip will have 2.5MB of on-chip memory and can shuttle data to and from off-chip memory at speeds up to 100 gigabytes per second, using XDR and FlexIO interface technology licensed from Rambus. "One of the key messages you hear from the architects of next-generation chips is that their performance is being limited by off-chip bandwidth," said Rich Warmke, Rambus, product marketing manager. "We've really licked that with Cell. 100GB per second is really unprecedented in the industry."

• The chip will have 234 million transistors, measure 221mm square and be produced using advanced 90-nanometer chipmaking processes.

While the PlayStation 3 is likely to be the first mass-market product to use Cell, the chip's designers have said the flexible architecture means Cell will be useful for a wide range of applications, from servers to cell phones. Initial devices are unlikely to be any smaller than a game console, however--the first version of the Cell will run hot enough to require a cooling fan, Kahle said.

Some competitors, however, are skeptical that Cell will find much of a home outside of video games. One of the big problems with Cell, said Justin Rattner, an Intel fellow, is that the processing units aren't identical, a situation that increases complexity and the opportunity for bugs.

"You've got this asymmetry," Rattner said. "It's like having two kinds of motors under the hood. We are very reluctant to adopt architectures like this because they take compatibility and throw it out the window."

[Colonel Cortez]

Sony PS3 Supercomputer Debut Affiliates

By Cornelius Wilson on 02/07/05

The cell "supercomputer" chip that powers the new PlayStation 3 games console is set to be unveiled today in San Francisco.

Sony, IBM and Toshiba have spent some $400 million developing the next generation cell chip for the past three years.

It is thought the super chip will be able to process a whopping 256 billion operations a second making the new chip around ten times faster than current processors.

The Times explains how it works: Whereas most existing microchips contain several cores that all work on the same task, the new chip is divided into entirely separate "cells" that can work independently on different tasks. What this means in practice is that computers linked together in a network can borrow unused processing power from each other, making the most efficient use of their computing capabilities. For example, if two PlayStation 3 consoles were connected via the internet, one could use part of the other's Cell chip to complete processor-intensive tasks such as downloading video content.

nah man, they are refering to a "network" not the internetr, a network such as in LAN or WLAN, sharing processing power online would be very extrmremly hard to do, but still possible

[SessDMC]

I mean WLAN sorry for the confusion, i mean sony cant make the internet with all its consoles, well not this generation.

[Schmeh]

I know it is alot of the same stuff that has been posted but here is some more info on the Cell. This is form Tom's Hardware.com

Cell processor to run at more than 4 GHz

By Wolfgang Gruener, Senior Editor

February 7, 2005 - 16:03 EST

San Francisco (CA) - UPDATE - IBM, Sony and Toshiba unveiled more details about their much anticipated Cell processor that is said to crush the performance of current AMD and Intel processors. The chip likely will debut in the Playstation 3 and top clock speeds of 4 GHz.

It wasn't quite the detail many attendees of ISSCC had hoped for, but IBM, Sony and Toshiba revealed enough information about their much-hyped Cell processor to spur discussion and speculation of the impact of the chip when it hits the market. The prototype shown at the conference is based on Power architecture, integrates nine cores and runs at "more than 4 GHz".
The basic structure of the chip is comprised out of one 64-bit PowerPC chip and eight "synergistic processing units" (SPEs), the firms said. The PowerPC processor will integrate 32 kByte L1 and 512 kByte L2 cache, while the SPEs will use 256 KByte cache.

The "operating system neutral" chip is manufactured in 90 nm SOI, has a 221 mm2 footprint and integrates 234 million transistors. This compares to about 125 million transistors of the current Pentium 4 processor, which measures 122 mm2. The memory and memory interface for the chip is designed by Rambus and will be built around the firm's FlexIO processor bus interface and XDR memory. The aggregate processor bandwidth of the Cell processor is estimated to top 100 GByte per second. According to Rambus, FlexIO is capable of running up to 6.4 GHz data rates providing bandwidth more than four times faster than best-of-class processor buses available today. XDR data rates will clocked from 3.2 GHz to 8.0 GHz, Rambus said.

The additional data provided still doesn't answer the question how capable the Cell chip will be in the end and which processor could be threatened, if the developer trio can deliver on its promise to build a "supercomputer on a chip". According to a statement, Cell will be about ten times faster than the "latest PC processors".

Analysts such as Dean McCarron from Mercury Research stressed that revolutionary chips such has the Cell processor had been announced in the past, but were not successful to post a major and lasting threat for the x86 architecture. According to IBM and Sony, Cell is targeted to become a "broadband processor" for industrial applications and the "digital home". Applications will include Sony's Playstation 3, high-end consumer electronics such as digital televisions and home entertainment systems and supercomputer-like workstations that promise multimedia developers significant more processing performance.

Industry watchers also expect the Cell chip to become available in a version for rack servers where the potentially could target next-generation Intel Itanium systems.

[Soad]

http://gear.ign.com/articles/585/585925p1.html

"Cell to Use Rambus""

[gaming ultima]

http://gear.ign.com/articles/585/585925p1.html

"Cell to Use Rambus""

everyone knows that cell based computers will use XDR and Redwood
we also know that the ps3 will use XDR and maybe Redwood
edit: ok they will be using FlexIO and not Redwood

[The_One]

The chip that will run the next version of the PlayStation video game machine will have nine processor cores and run faster than 4GHz, the chip's designers revealed Monday.

Nine cores? What the heck? What kind of odd number is that? Is this a mistake on that GameSpot reporter's side? As far as I know, devs doesn't like to work with odd numbers (one good reason why sprite based games used 32x32 sprites instead of 31x31), and I'm quite sure nine "cores" would be a surprise also -- that's IF it's not a mistake.

On top of that, what do they mean by "cores"? PE, PU, or APU's? My take is APU's (obviously), but it's kinda obvious that the reporter doesn't really have an idea of what a "core" is.

[gaming ultima]

The chip that will run the next version of the PlayStation video game machine will have nine processor cores and run faster than 4GHz, the chip's designers revealed Monday.

Nine cores? What the heck? What kind of odd number is that? Is this a mistake on that GameSpot reporter's side? As far as I know, devs doesn't like to work with odd numbers (one good reason why sprite based games used 32x32 sprites instead of 31x31), and I'm quite sure nine "cores" would be a surprise also -- that's IF it's not a mistake.

On top of that, what do they mean by "cores"? PE, PU, or APU's? My take is APU's (obviously), but it's kinda obvious that the reporter doesn't really have an idea of what a "core" is.

he and everybody else that talks about 9 cores means 1 PU + 8 APU's
edit: and when they talk about 1 cell they mean a PE

[The_One]

Ah, thanks for the clear up. And yes, I know CELL = 1 PE. I know at least that .

[Schmeh]

I am not sure if these should go here or a new thread, but here are some pics of the cell. They are from Electronicsweekly.com


A Cell SPE


The entire Cell

[The_One]

Those are kind of unclear... Let me post some clear ones:




EDIT: Also, a CELL is comprised of a PE... So I'm not sure what you meant by one being the "Complete CELL" and one being the "CELL PE"... .

EDIT 2: Ops, looks like gaming ultima got to it before I could edit :P.

[gaming ultima]

edit your post, the top pic is of a SPE or APU not a PE
the bottom pic is of a PE

[Schmeh]

Those are kind of unclear... Let me post a clear one:
http://img138.exs.cx/img138/9104/cell3jb8fq.jpg
Also, a CELL is comprised of a PE... So I'm not sure what you meant by one being the "Complete CELL" and one being the "CELL PE"... .

My pics were posted to show the inner workings of the chip, and by "Complete Cell" I meant one chip.

[The_One]

Those are kind of unclear... Let me post a clear one:
http://img138.exs.cx/img138/9104/cell3jb8fq.jpg
Also, a CELL is comprised of a PE... So I'm not sure what you meant by one being the "Complete CELL" and one being the "CELL PE"... .

My pics were posted to show the inner workings of the chip, and by "Complete Cell" I meant one chip.

No, that's not what I meant. You seem to not understand what a CELL is. All ONE CELL is, is simply that, a PE. A PE is the Processing Element, and it then comprise of 1 PU, which has 8 APU's attached to it.

To put simply: CELL = PE
So those two cannot have two "different" pictures.

[gaming ultima]

have a read of this -
"With the promise of incredible performance and scalability, and what is basically a vector supercomputer on a chip, we present the 2004 Microprocessor Report Analysts' Choice Award for Best Technology to the Cell Processor. Congratulations to the STI Design Center and the participating employees at IBM, Sony, and Toshiba for what promises to be a very exciting challenge to mainstream processors."

http://www.electronicsweekly.com/art...earch=&nPage=1

[The_One]

gaming ultima... You find the GREATEST news of anyone I know ... Oh man... That is RICH... RICH!!!!!!! I think they just might be sued for slander . ROFLMA.... sorry, hehe :P.

Here's a higher resolution pic I found:

[Schmeh]

Those are kind of unclear... Let me post a clear one:
http://img138.exs.cx/img138/9104/cell3jb8fq.jpg
Also, a CELL is comprised of a PE... So I'm not sure what you meant by one being the "Complete CELL" and one being the "CELL PE"... .

My pics were posted to show the inner workings of the chip, and by "Complete Cell" I meant one chip.

No, that's not what I meant. You seem to not understand what a CELL is. All ONE CELL is, is simply that, a PE. A PE is the Processing Element, and it then comprise of 1 PU, which has 8 APU's attached to it.

To put simply: CELL = PE
So those two cannot have two "different" pictures.

You are right. I edited my post to reflect just that. The first pic is of the APU and the second pic is of the entire Cell or 1 PU and 8 APUs.

[The_One]

Also, someone on PSiNext posted this (I take no credit for it, I'm not a plagiariser :P).

From www.electronicsweekly.com image of SPE I can make out these unit names.

Basic layout of a CELL APU/SPE (not to scale)

+---------------+--------------+-------------+
| Single        |      DP      |     LS3     |
| Precision     |              |             |
+---------------+--------------+-------------+
| Simple Fixed  |    channel   |     LS2     |
+---------------+--------------+-------------+
| Forward Macro |              |             |
+---------------+    branch    |     LS1     | 
| Permute       |              |             |
+---------------+--------------+-------------+
|               |    issue     |             |     
|   GPR         |   control    |     LS0     |
|               +--------------+             | 
|               |   TLB/ILB?   |             |
+---------------+--------------+-------------+
|               |  channel     |             |
| DMA           +--------------+   channel   +
|               |              +-------------+ 
+---------------+    MMU       |     ATO     |
|               +--------------+-------------+ 
|                BIU?          |     RTB     |
+------------------------------+-------------+

From the die patterns I would say that the following units are 4-way SIMD:
Single Precision (32bit float)
Simple fixed (32bit int / fixed point formats)
Forward Macro (no idea what this might do)
Permute (component swizzling I guess)

The DP (Dual precision, 64bit double, I'm guessing) is only 2 way, but then that makes sense (2 64bit doubles in a register).

I'm guessing all of these units can execute simultaneously, but have different latencies (depending on instruction, e.g. divide is high latency). And it appears the SPE can issue 2 instructions per clock, that sounds good, but I'll wait for confirmation on that.

I wonder if it can execute 4way 32bit float and 2way 64bit double precision per cycle? I certainly imagine it could execute single precision and simple fixed simultaneously.

Would like to know what the ATO, BIU and RTB are?
And channel?

And that unit left of LS0. I am assuming LS stands for Local Storage and is SRAM.

Also noticed the SPE is referred to as 64bit... so does that mean 64bit instruction word? I'd certainly expect it'll need 64bits to encode all those registers.

It's looking like one beast of a processor, I really hope the PS3 has more than 8 though. Would like to a see 16/32 SPEs (4 BEs) CELL configuration.

It's looking like one beast of a processor, I really hope the PS3 has more than 8 though. Would like to a see 16/32 SPEs (4 BEs) CELL configuration.

Indeed... That would be the only possibly way of reaching the 1 TFLOp/s mark.

I'm guessing all of these units can execute simultaneously, but have different latencies (depending on instruction, e.g. divide is high latency). And it appears the SPE can issue 2 instructions per clock, that sounds good, but I'll wait for confirmation on that.

The SPE's can issue 2 instructions per clock, hey, that sounds almost as good as P4's :P (I believe the P4's can issue 2 instructions, but per ever other clock.)!